What is the function of hysteresis in a comparator?

1. A To prevent input noise from causing unstable output signals
2. B To allow the comparator to be used with AC input signals
3. C To cause the output to continually change states
4. D To increase the sensitivity

What happens when the level of a comparator's input signal crosses the threshold voltage?

1. A The IC input can be damaged
2. B The comparator changes its output state
3. C The reference level appears at the output
4. D The feedback loop becomes unstable

What is tri-state logic?

1. A Logic devices with 0, 1, and high-impedance output states
2. B Logic devices that utilize ternary math
3. C Logic with three output impedances which can be selected to better match the load impedance
4. D A counter with eight states

Which of the following is an advantage of BiCMOS logic?

1. A Its simplicity results in much less expensive devices than standard CMOS
2. B It is immune to electrostatic damage
3. C It has the high input impedance of CMOS and the low output impedance of bipolar transistors
4. D All these choices are correct

Which of the following digital logic families has the lowest power consumption?

1. A Schottky TTL
2. B ECL
3. C NMOS
4. D CMOS

Why do CMOS digital integrated circuits have high immunity to noise on the input signal or power supply?

1. A Large bypass capacitance is inherent
2. B The input switching threshold is about twice the power supply voltage
3. C The input switching threshold is about half the power supply voltage
4. D Bandwidth is very limited

What best describes a pull-up or pull-down resistor?

1. A A resistor in a keying circuit used to reduce key clicks
2. B A resistor connected to the positive or negative supply used to establish a voltage when an input or output is an open circuit
3. C A resistor that ensures that an oscillator frequency does not drift
4. D A resistor connected to an op-amp output that prevents signals from exceeding the power supply voltage

In Figure E6-3, which is the schematic symbol for a NAND gate?

1. A 1
2. B 2
3. C 3
4. D 4

What is used to design the configuration of a field-programmable gate array (FPGA)?

1. A Karnaugh maps
2. B Hardware description language (HDL)
3. C An auto-router
4. D Machine and assembly language

In Figure E6-3, which is the schematic symbol for a NOR gate?

1. A 1
2. B 2
3. C 3
4. D 4

In Figure E6-3, which is the schematic symbol for the NOT operation (inversion)?

1. A 2
2. B 4
3. C 5
4. D 6