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E6C07

CIRCUIT COMPONENTS · Digital ICs: families of digital ICs; gates; programmable logic devices

E6C07E6C →

What best describes a pull-up or pull-down resistor?

  1. AA resistor in a keying circuit used to reduce key clicks
  2. BA resistor connected to the positive or negative supply used to establish a voltage when an input or output is an open circuit
  3. CA resistor that ensures that an oscillator frequency does not drift
  4. DA resistor connected to an op-amp output that prevents signals from exceeding the power supply voltage
Why Digital inputs are high impedance, so if nothing actively drives them they float and pick up noise, reading randomly high or low. A pull-up resistor ties the line to V+ and a pull-down ties it to ground, so the line sits at a defined logic level whenever the driving device is open circuit (for example a switch that is not closed, or an open-collector/open-drain output). Typical values are a few kilohms: high enough not to waste current, low enough to overcome leakage and noise.
Watch out The key-click choice describes RC shaping of a CW keying waveform, which is a transmitter filtering issue and has nothing to do with defining a logic level on a floating line.
Pull-up/pull-down = give a floating input a home. Up to V+, down to ground.
HamSandwich explanation, first draft. The question and answers are the NCVEC text.
← E6C06 All of E6C E6C08 →

The rest of E6C

  1. E6C01 What is the function of hysteresis in a comparator?
  2. E6C02 What happens when the level of a comparator's input signal crosses the threshold voltage?
  3. E6C03 What is tri-state logic?
  4. E6C04 Which of the following is an advantage of BiCMOS logic?
  5. E6C05 Which of the following digital logic families has the lowest power consumption?
  6. E6C06 Why do CMOS digital integrated circuits have high immunity to noise on the input signal or power supply?
  7. E6C07 What best describes a pull-up or pull-down resistor?
  8. E6C08 In Figure E6-3, which is the schematic symbol for a NAND gate?
  9. E6C09 What is used to design the configuration of a field-programmable gate array (FPGA)?
  10. E6C10 In Figure E6-3, which is the schematic symbol for a NOR gate?
  11. E6C11 In Figure E6-3, which is the schematic symbol for the NOT operation (inversion)?
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