E6C08
CIRCUIT COMPONENTS · Digital ICs: families of digital ICs; gates; programmable logic devices
E6C08E6C →
In Figure E6-3, which is the schematic symbol for a NAND gate?
- A1
- B2
- C3
- D4
Why A NAND gate is simply an AND gate followed by an inverter, so its symbol is the AND body, a flat back with a half-round or D-shaped front, plus a small bubble (circle) at the output that means inversion. Symbol 2 in Figure E6-3 has that D-shaped AND body with the inverting bubble, so it is the NAND. Its output is low only when all inputs are high, the exact complement of AND.
Watch out Symbol 1 is the same D-shaped body without the output bubble, which is a plain AND gate; the curved, shield-shaped bodies in the figure are the OR family.
Shape tells AND vs OR (D = AND, shield = OR); bubble on the output adds the N in NAND/NOR.
HamSandwich explanation, first draft. The question and answers are the NCVEC text.
The rest of E6C
- E6C01 What is the function of hysteresis in a comparator?
- E6C02 What happens when the level of a comparator's input signal crosses the threshold voltage?
- E6C03 What is tri-state logic?
- E6C04 Which of the following is an advantage of BiCMOS logic?
- E6C05 Which of the following digital logic families has the lowest power consumption?
- E6C06 Why do CMOS digital integrated circuits have high immunity to noise on the input signal or power supply?
- E6C07 What best describes a pull-up or pull-down resistor?
- E6C08 In Figure E6-3, which is the schematic symbol for a NAND gate?
- E6C09 What is used to design the configuration of a field-programmable gate array (FPGA)?
- E6C10 In Figure E6-3, which is the schematic symbol for a NOR gate?
- E6C11 In Figure E6-3, which is the schematic symbol for the NOT operation (inversion)?