Why do CMOS digital integrated circuits have high immunity to noise on the input signal or power supply?
Why CMOS logic inputs switch state when the input passes roughly 50% of the supply rail (Vdd/2), so a logic low can drift upward by nearly half the supply and a logic high can droop by nearly half before the gate misreads it. That symmetric, wide noise margin on both the high and low sides is what gives CMOS its noise immunity, and because the threshold tracks the supply, supply variation shifts the threshold along with the signal levels. By contrast, TTL thresholds sit near 1.4 V on a 5 V rail, leaving much less margin on the low side.
Watch out The claim that the threshold is about twice the supply voltage is impossible, since no input driven from the same supply could ever reach that level and the gate would never switch. Bypass capacitance is added externally, not inherent, and limited bandwidth is not why CMOS resists noise.
CMOS switches at half the rail: about half the supply of noise margin on each side.